Memory response time is failing to keep up with the pace of today’s processing technology. This means the processor is often forced to stall and wait for data to load from memory, this is known as a load stall. While caches attempt to remedy this imbalance by making future requests for data easily accessible, they require temporal and spatial locality to work effectively. When they do not, the cache miss rate can spike and cause performance degradation. Manually optimizing programs for cache performance is a taxing and error-prone process, rendered more complex by the fact most programs are written in high-level languages where the programmer does not have fine control of memory, e.g. Java. Therefore, this project aims to study the impact of load stalls in Java workloads and design impact mitigation strategies. We first gathered and analyzed data on load stalls from several commonly used hardware architectures. Based on the results of our survey, we designed a micro benchmark suite that can be used to get deeper insights into various load mitigation strategies.

Ken Kent, Professor & Barrett Chair in Entrepreneurship for Digital Transformation, University of New Brunswick

Julian Wang, Senior Developer, IBM

Activity Type: Technology Breakout
Technical Level: Intermediate Level