IBM Z and LinuxONE Languages

Languages

Languages

Broad range of supported development languages and tools allows to transform software delivery practices.

 View Only

  • 1.  Metal C - routine entry linkage question

    Posted Fri January 10, 2020 05:27 PM
    Edited by Scott Fagen Mon January 13, 2020 11:32 AM
    I'm writing my own Metal C entry prolog/epilog and was trying to ensure that I do everything that the compiler would do, so I took a look what was generated for entry linkage for a routine that is defined to run in AR mode (F7SA).  Here's what was generated, with my annotations.  Can anyone explain what the code in red is accomplishing?
    ADDTOCHA DS 0F
             CPYA 15,13              --- remember the ALET to the caller's SA/DSA
             LAE 13,0(,13)           --- if called from primary mode, clears AR13, otherwise preserves ALET
             STAM 15,15,204(13)      --- Save caller's R13 in SA
             STMG 14,12,8(13)        --- Save caller's GPRs in SA
             STAM 14,12,144(13)      --- Save caller's ARs in SA
             IAC 11                  --- Get caller's ASC mode
             ST 11,208(,13)          --- Save caller's ASC mode in SA
             SAC 512                 --- Get into AR ASC mode
             LGR 15,13               --- Get address of caller's SA
             LG 13,136(,13)          --- Get address of NAB (new SA/DSA) from caller's SA
             STG 15,128(,13)         --- Back chain new SA to caller's SA
             ST 15,4(,13)            --- ??? (appears to be some sort of carryover from F1SA back chain to caller's SA???)
             LAE 1,0(,1)             --- ??? (is essentially a NOP in AR mode, the GPR and AR will not change???)
    @@BGN@8  DS 0H
             LLILH 11,X'C6F7'        --- Stuff 'F7' into R11
             OILL 11,X'E2C1'         --- Stuff 'SA' into R11
             ST 11,4(,13)            --- Stuff 'F7SA' into new save area (note that this will overlay the data from the ST 15,4(13) from the red highlighted code above)


    ------------------------------
    Scott Fagen
    scottf@21csw.com
    ------------------------------


  • 2.  RE: Metal C - routine entry linkage question

    Posted Tue January 14, 2020 08:48 AM
    Greetings,
    I am Language Environment Level 3 team member. Thank you for posting the question in the community.

    Seems the prolog you referred to is the default prolog for AR-mode function.

    'z/OS Metal C Programming Guide and Reference' describes the prolog in section 'Default prolog and epilog code for AR-mode functions'.
    For AR-mode functions, the default prolog code generates additional instructions that:
       Save the calling function's access registers in the F7SA save area.
       Save the ASC mode of the calling function in the F7SA save area.
       Switch to AR mode.
       Prime AR 1 and AR 13 with LAE instructions.

    ST 15,4(,13) --- The 'ST' seems useless under your situation. May I know the compile options you used?
                                   I tried 31bit and 64bit Metal C, but I didn't get result like yours.
                                   For 31bit, the ST is generated and the field 4(,13) is used later in epilog.
                                   For 64 bit, the ST instruction is not generated.

    LAE 1,0(,1) --- Don't know why but the default prolog mentions 'Prime AR 1 and AR 13 with LAE instructions', we may should follow it.

    The following links about F7SA example and 'Metal C AR-mode programming support' may help on coding your own prolog and epilog code:
    https://www.ibm.com/support/knowledgecenter/en/SSLTBW_2.4.0/com.ibm.zos.v2r4.ieaa600/changear.htm
    https://www.ibm.com/support/knowledgecenter/en/SSLTBW_2.4.0/com.ibm.zos.v2r4.ccrug00/armodefuncs.htm

    ---------------------------------------------
    Some test results:
    1. 64 bit compile: xlc -S -qmetal -qNOSEARCH -qARMODE -qlist -q64 -I /usr/include/metal/ mc.c
    In 64 bit list, the ST instruction is not generated:

    2. 31 bit compile: xlc -S -qmetal -qNOSEARCH -qARMODE -qlist -I /usr/include/metal/ mc.c
    In 31 bit list, the ST instruction is generated:


    ------------------------------
    He Huang
    ------------------------------

    Original Message


  • 3.  RE: Metal C - routine entry linkage question

    Posted Thu January 16, 2020 09:42 AM
    He,

    Thank you for your continued support!

    Per:

    ST 15,4(,13) --- The 'ST' seems useless under your situation. May I know the compile options you used?
                                   I tried 31bit and 64bit Metal C, but I didn't get result like yours.
                                   For 31bit, the ST is generated and the field 4(,13) is used later in epilog.
                                   For 64 bit, the ST instruction is not generated.

    The compiler options (gleaned from the listing) were:
    *NOGONUMBER *NOALIAS *NORENT *TERMINAL *NOUPCONV *SOURCE *LIST
    *XREF *NOAGG *NOPPONLY *NOEXPMAC *NOSHOWINC *NOOFFSET *MEMORY *SSCOMM
    *NOSHOWMACROS *SKIPSRC(HIDE) *NOREPORT *NOMAKEDEP *PREFETCH *THREADED
    *NOLONGNAME *START *EXECOPS *ARGPARSE *NOEXPORTALL*NODLL(NOCALLBACKANY)
    *NOLIBANSI *NOWSIZEOF *REDIR *ANSIALIAS *DIGRAPH *NOROCONST *ROSTRING
    *TUNE(7) *ARCH(7) *SPILL(128) *MAXMEM(2097152) *NOCOMPACT
    *TARGET(LE,CURRENT) *FLAG(I) *NOTEST(SYM,NOBLOCK,NOLINE,NOPATH,NOHOOK) *NOOPTIMIZE
    *INLINE(AUTO,NOREPORT,100,1000) *NESTINC(255) *BITFIELD(UNSIGNED)
    *NOINFO
    *NODFP
    *NOVECTOR
    *FLOAT(IEEE,FOLD,NOMAF,NORRM,AFP(NOVOLATILE)) *ROUND(N)
    *STRICT
    *NOCOMPRESS *NOSTRICT_INDUCTION *AGGRCOPY(NOOVERLAP) *CHARS(UNSIGNED)
    *NOIGNERRNO
    *NOINITAUTO
    *CSECT
    *NOEVENTS
    *ASSERT(RESTRICT)
    *NORESTRICT
    *NOOBJECT
    *GENASM
    *OPTFILE(//'TLN.V200.PSOURCE(TLNMCOPT)')
    *NOSERVICE
    *NOOE
    *NOIPA
    *SEARCH(/usr/include/metal/, 'CBC.SCCNSAM')
    *LSEARCH('TLN.V200.PSOURCE.H', 'TLN.V200.PSOURCE.CHDSECT', 'C21S.METALC.ZOS21.CHDSECT',
    'C21S.METALC.MODGEN21.CHDSECT')
    *NOLOCALE *HALT(16) *PLIST(HOST)
    *NOCONVLIT
    *NOASCII
    *NOGOFF *ILP32 *NOWARN64 *HGPR(PRESERVE) *NOHOT *METAL *NOARMODE
    *NOXPLINK(NOBACKCHAIN,NOSTOREARGS,NOCALLBACK,GUARD,OSCALL(NOSTACK))
    *ENUMSIZE(SMALL)
    *NOHALTONMSG
    *NOSUPPRESS
    *RESERVED_REG(R12)
    *NORTCHECK
    *NODEBUG
    *NOSQL
    *NOCICS
    *UNROLL(AUTO)
    *KEYWORD()
    *NOKEYWORD(asm,typeof)
    *NOSEVERITY
    *NODSAUSER
    *NOINCLUDE
    *NOSMP
    *SYSSTATE(NOASCENV,OSREL(NONE))
    *NOFUNCEVENT
    *ASM

    Per:
    LAE 1,0(,1) --- Don't know why but the default prolog mentions 'Prime AR 1 and AR 13 with LAE instructions', we may should follow it.

    This instruction is preceded by a SAC 512, meaning the program is executing in AR ASC mode at the time of the LAE.  If my rusty assembler knowledge is correct, what this will do is take the value in the the base register and it's AR, update the address subject to the index and offset (both of which are 0 in this case) and put the result in the first register.  R1+0 (index)+0 (offset) = R1.  Since we are in AR mode, the system will propagate AR1 into AR1, so this instruction is effectively doing nothing.  

    If the ASC mode was primary (SAC 0), then this instruction would have had the effect of preserving R1 and setting AR1 to zero.

    Thoughts?

    Thanks,
    Scott


  • 4.  RE: Metal C - routine entry linkage question

    Posted Fri January 17, 2020 12:50 AM
    Hi Scott,

    I noticed that *NOARMODE compile option is used, so I guess you are using ' __attribute__((armode)) ' for specific function. Then I removed compile option ' -qARMODE ' and tested ' __attribute__((armode)) ', but I still got the same listing results as before.

    If it is convenient for you, please send your testcase and compile JCL/command to my email hbjhuang@cn.ibm.com . I would figure out what leads to the prolog/epilog (which didn't match the 31bit or 64bit results although they are all F7SA) and whether it's reasonable. Also, I wonder the z/OS version and z/OS XL C version.

    And I agree with your analysis about 'LAE 1,0(,1)', I just would mention that the LAE instruction might do something more under different conditions. One is address computations (for R1 in this case) under different addressing mode. Another is that, when PSW Bits 16 and 17 is 01 (AR mode), the value placed in Access Register will depend on the value in 'B2 field'.
    The manual for instructions: http://publibfi.boulder.ibm.com/epubs/pdf/dz9zr011.pdf

    ------------------------------
    He Huang
    ------------------------------

    Original Message


  • 5.  RE: Metal C - routine entry linkage question

    Posted Fri January 17, 2020 08:13 PM
    Hi He,

    I no longer have the original job (this was done months ago), but I can cut&paste information from the compiled listing:

    15650ZOS V2.1.1 z/OS XL C 'TLN.V200.PSOURCE.C(TLNCUSDT)' 07/17/2019 13:25:53 Page 1

    Compile Time Library . . . . . . : 42010000

    Version Macros. . . . . . . . : __COMPILER_VER__=0x42010001 __LIBREL__=0x42010000 __TARGET_LIB__=0x42010000
    Language level. . . . . . . . : *EXTENDED:NOTEXTAFTERENDIF
    Source margins. . . . . . . . :
    Varying length. . . . . . . : 1 - 32760
    Fixed length. . . . . . . . : 1 - 32760
    Sequence columns. . . . . . . :
    Varying length. . . . . . . : none
    Fixed length. . . . . . . . : none


  • 6.  RE: Metal C - routine entry linkage question

    Posted Tue January 14, 2020 08:48 AM
    Edited by He Huang Tue January 14, 2020 08:16 PM
    Deleting the duplicate reply ...


Related Content