XML is an incredibly useful data format for enterprise level applications. A diverse and robust set of tools and a time proven infrastructure have been developed across many platforms to facilitate application development. But a common concern about XML is that it tends to be compute intensive.  z/OS includes a very efficient XML parser component called z/OS XML System Services, which addresses many of the computing issues involved with XML parsing. Even so, we are constantly looking for new ways to improve performance.

With the new z13 mainframe, we looked for ways to use the new hardware features to improve XML parsing. One of the great new features is the single instruction, multiple data (SIMD) architecture. The new processor architecture includes 32 registers, each of which are a full 16 bytes wide. To operate on these registers, there is a full featured set of vector instructions which can operate on multiple operands at one time. Indeed, they can perform up to 16 simultaneous arithmetic, logical, or floating point operations. But the instructions which are the most interesting for XML parsing are the vector string instructions.

Why are vector string instructions so interesting? Well, in order to be compliant with the industry standard XML specifications, each character in an XML document must be checked to make sure it complies with the parsing rules. These rules are different depending on which structures are being examined at any one time. For example, element names have different parsing rules than attribute values. This means that the parsing code becomes more complex, and therefore more processor intensive. Fortunately, we can use the new Vector String Range Compare (VSTRC) instruction! This incredible instruction can perform multiple byte range tests simultaneously on up to 16 sequential bytes. The way this works is the code loads up two vector registers with the comparison specification, then loads up another vector register with the next set of 16 bytes of XML document data. The VSTRC instruction is then invoked, performs the range tests, and the results are placed into yet another vector register. A simple Condition Code check tells the program whether the string passes or not, and if so can move on to the next set of 16 bytes of XML data.

Due to the nature of the vector instructions, the greatest performance advantage is realized when operating on longer strings. These include various XML structures such as tag names, attribute names, character content and attribute values. Documents largely made up of strings which are 16 bytes or longer will show the best improvement. On the other hand, if the documents typically have short strings, then there will probably not be any improvement by using these new instructions.

To enable the XML System Services parser to use vector instructions, your application simply needs to specify the new feature flag, XEC_FEAT_ALLOW_VECTOR for assembler code or GXLHXEC_FEAT_ALLOW_VECTOR for C code on the parser initialization API call. The application doesn't even need to check for the presence of the SIMD architecture. The parser will check if the capability is present, and if not, it will use the non-SIMD support.  This new feature is supported only for non-validating parsing applications.  It is available in z/OS 2.2, and was rolled back to z/OS 2.1 in the beginning of this year.